1. Field of the Invention
This invention relates to JFET integrated circuits (ICs) comprising a substrate carrying JFETs together with other circuit elements. More particularly, this invention relates to such ICs having means to reduce damage to the JFETs from the effects of electrostatic discharge (ESD).
2. Prior Art
It is well known that ICs are subject to serious damage or destruction as a result of Electrostatic Discharge (ESD) events. The electrostatic voltage associated with the discharge can be developed by any of many sources, including lightning, or friction between insulating bodies such as synthetic fiber clothing. Damage occurs when the ESD voltage is accidentally coupled to one of the circuit terminals and thence to some portion of the metal interconnect layer of the IC.
The metal interconnect is typically an Aluminum layer laid down over an oxide coating overlying the top surface of the semiconductor. The ESD voltage can cause a current to flow from the metal through various potential paths where the current flow can cause damage. For example, the voltage can be sufficient to break down the oxide coating to allow current to flow through to the underlying semiconductor. Still other paths are available for current flow. The current ultimately leaves the IC through some other circuit terminal. The magnitude of the current is often sufficient to cause significant damage, e.g. by leaving an oxide coating permanently conducting, and the resulting shunt path causing circuit failure.
Various techniques have been developed to prevent damage from ESD events. For Example, the sensitivity to ESD events in ICs can be reduced by altering the position of the metal interconnect, by changing the layout of the impurity depositions, or widening resistors. Also, separate protection networks have been employed in some cases.
JFETs are especially sensitive to damage from ESD events. The problem of JFET sensitivity to ESD events cannot be solved by known techniques such as by rearranging layouts and the like, and protection networks are unsatisfactory because they degrade JFET performance excessively. Accordingly, protecting JFETs from ESD events has represented a serious problem. It is the purpose of this invention to solve that problem.